1 document # sram108 rev or revised october 2005 features high speed (equal access and cycle times) ? 10/12/15/20/25/35 ns (commercial) ? 15/20/25/35 ns (military) cmos for low power ? 495 mw max. ? 10/12/15/20/25 (commercial) ? 495 mw max. ? 15/20/25/35 (military) description the p4c423 is a 1,024-bit high-speed (10ns) static ram with a 256 x 4 organization. the memory requires no clocks or refreshing and has equal access and cycle times. inputs and outputs are fully ttl compatible. operation is from a single 5 volt supply. easy memory expansion is provided by an active low chip select one ( cs 1 ) and active high chip select two (cs 2 ) as well as 3-state outputs. p4c423 high speed 256 x 4 static cmos ram functional block diagram pin configuration in addition to high performance and high density, the device features latch-up protection, single event and upset protection. the p4c423 is offered in a 24-pin 300 mil dip. devices are offered in both commercial and military temperature ranges. single 5v10% power supply separate i/o fully ttl compatible inputs and outputs resistant to single event upset and latchup result ing from advanced process and design improvements standard 24-pin 300 mil dip package. dip (c4)
p4c423 page 2 of 8 document # sram108 rev or dc electrical characteristics over recommended operating temperature and supply voltage (2) p4c422 min max v oh output high voltage i oh = ?5.2 ma, v cc = min.2.4 v v ol output low voltage i ol = +8 ma, v cc = min. 0.4 v v ih input high voltage 2.1 v v il input low voltage 0.8 v v cl input clamp diode voltage i in = ?10 ma ?1.5 v i ix input load current gnd v in v cc ?10 10 a i oz output current (high z) v ol v out v oh , output disabled ?10 10 a i os output short circuit v cc = max., v out = gnd 90 ma current (3) grade (2) ambient temp gnd vcc commercial 0c to 70c 0v 5.0v 10% military ? 55c to 125c 0v 5.0v 10% symbol parameter test conditions unit symbol parameter conditions typ. unit c in input capacitance v in = 0v 5 pf c out output capacitance v out = 0v 7 pf capacitances (4) (v cc = 5.0v, t a = 25c, f = 1.0mhz) recommended operating conditions symbol parameter value unit t bias temperature under ? 55 to +125 c bias t stg storage temperature ? 65 to +150 c i out dc output current 20 ma maximum ratings (1) symbol parameter value unit v cc power supply pin with ? 0.5 to +7 v respect to gnd terminal voltage with ? 0.5 to v term respect to gnd v cc +0.5 v (up to 7.0v) t a operating temperature ? 55 to +125 c notes: 1. stresses greater than those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to maximum rating conditions for extended periods may affect reliability. 2. extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3. for test purposes, not more than one output at a time should be shorted. short circuit test duration should not exceed 30 seconds. 4. this parameter is sampled and not 100% tested. 5. transition time is 3ns for 10, 12, and 15 ns products and 5ns for 20, 25, and 35 ns products, see fig 1d. timing is referenced at input and output levels of 1.5v. the output loading is equivalent to the specified i ol /i oh with a load capacitance of 15 pf (10, 12) or 30 pf (15, 20, 25, 35) as in fig. 1a and 1b respectively. 6. transition time is 3ns for 10, 12, and 15 ns products and 5ns for 20, 25, and 35 ns products, see fig 1d. transition is measured at steady state high level -500mv or steady state low level +500mv on the output from a level on the input with load shown in fig. 1c. 7. t w is measured at t wsa = min.; t wsa is measured at t w = min. power dissipation characteristics vs. speed symbol i cc parameter dynamic operating current temperature range commercial military -10 90 n/a -12 90 n/a -15 90 90 -20 90 90 -25 65 90 -35 65 90 unit ma ma
p4c423 page 3 of 8 document # sram108 rev or mode cs 2 cs cs cs cs cs 1 we we we we we oe oe oe oe oe output standby l x x x high z standby x h x x high z d out disabled h l x h high z read h l h l d out write h l l x high z recovery times by eliminating the ?write recovery glitch.? reading is performed with chip selct one ( cs 1 ) low, chip select two (cs 2 ) high, write enable ( we ) high and output enable ( oe ) low. the information stored in the addressed word is read out on the noninverting outputs (o 0 through o 3 ). the outputs of the memory go to an inactive high impedance state whenever chip select one ( cs 1 ) is high, or during the write operation when write enable ( we ) is low. an active low write enable ( we ) controls the writing/ reading operation of the memory. when the chip select one ( cs 1 ) and the write enable ( we ) are low and the chip select two (cs 2 ) is high, the information on data inputs (d 0 through d 3 ) is written into the addressed memory word and preconditions the output circuitry so that true data is present at the outputs when the write cycle is complete. this preconditioning operation insures minimum write functional description truth table ac electrical characteristics?read cycle (v cc = 5v 10% except as noted, all temperature ranges) (2) timing waveform of read cycle notes: h = high l = low x = don't care high z = implies outputs are disabled or off. this condition is defined as high impedance state for the p4c422. sym. t rc t acs t zrcs t aos t zros t aa read cycle time (5) chip select time (5) chip select to high-z (6) output enable time output enable to high-z (6) address access time (5) -10* min max 7.5 8 7.5 8 10 -12 min 12 max 8 10 8 10 12 -15 min 15 max 8 12 8 12 15 -20 min 20 max 12 15 12 15 20 -25 min 25 max 15 20 15 20 -35 min 35 max unit ns ns ns ns ns ns 25 *v cc = 5v 5% 25 30 25 30 35 parameter 12
p4c423 page 4 of 8 document # sram108 rev or max ac characteristics?write cycle (v cc = 5v 10% except as noted, all temperature ranges) (2) timing waveform of write cycle parameter write cycle time (5) write enable to high-z (6) write recovery time write pulse width (5,7) data setup time prior to write (5) data hold time (5) address setup time (5,7) address hold time (5) chip select setup time (5) chip select hold time (5) sym. t wc t zws t wr t w t wsd t whd t wsa t wha t wscs t whcs -10* -12 -15 -20 -25 -35 unit min max min max min max min min max min max 10 8 0 2 8 8 12 9 0 10 10 15 11 0 2 12 12 20 13 2 15 15 25 15 5 20 20 35 20 5 30 25 ns ns ns ns ns *v cc = 5v 5% 225 55ns 00 0 25 5 ns 22 4 55 5 ns 0 00255ns 22 5 5 5ns
p4c423 page 5 of 8 document # sram108 rev or figure 1c figure 1d figure 1a figure 1b ac test loads & waveforms
p4c423 page 6 of 8 document # sram108 rev or *military temperature range with mil-std-883, class b compliance. n/a = not available selection guide the p4c423 is available in the following temperature range, speed, and package options. ordering information 10 12 15 20 25 35 commercial temperature side brazed dip -10cc -12cc -15cc -20cc -25cc -35cc military temperature side brazed dip n/a n/a -15cm -20cm -25cm -35cm military processed* side brazed dip n/a n/a -15cmb -20cmb -25cmb -35cmb speed (ns) temperature range package
p4c423 page 7 of 8 document # sram108 rev or side brazed dual in-line package pkg # # pins symbol min max a - 0.200 b 0.014 0.026 b2 0.045 0.065 c 0.008 0.018 d - 1.280 e 0.220 0.310 ea e l 0.125 0.200 q 0.015 0.060 s1 0.005 - s2 0.005 - 0.100 bsc c4 24 (300 mil) 0.300 bsc
p4c423 page 8 of 8 document # sram108 rev or revisions document number : sram108 document title : p4c423 high speed 256 x 4 static cmos ram rev. issue date orig. of change description of change orig 1997 jdb new data sheet
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